A semiconductor device includes a base and a semiconductor chip bonded to the base through a solder layer made of solder material. Here, the base is formed of a circuit board. Solder material between the chip and the base is heated and reflowed so that the solder layer is formed. Thus, the semiconductor chip and the base are bonded together.
When the device is operated, the semiconductor chip generates heat. The heat is discharged from the base through the solder layer. However, when the solder layer includes voids, heat radiation path is disturbed by the voids, so that the heat is not effectively discharged. Thus, the temperature of the chip increases, and therefore, the temperature of the chip may exceed over the maximum allowable temperature of the chip. Accordingly, cooling performance of the chip is decreased by the voids.
A method for bonding the chip on the base with reducing the voids in the solder layer is disclosed in, for example, Japanese Laid-open Patent Publication No. H6-23534, which corresponds to U.S. Pat. No. 5,361,973.
However, it is difficult to remove the voids from the solder layer completely.
Further, there is no disclosure to bond the chip on the base with high cooling performance of the chip even when the voids exist in the solder layer. Specifically, in a prior art, there is no disclosure regarding influence of the voids in the solder affecting to the cooling performance of the chip, and there is no disclosure of study about an position of the void and a diameter of the void in the solder layer.